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Learn MoreIntroduction to VHDL for FPGA and ASIC design
What you'll learn
- Practical FPGA and ASIC RTL design using VHDL
Explore related topics
Course content
6 sections • 26 lectures • 9h 19m total length
- Why VHDL23:48
In the first lecture of the course we discuss why Hardware Description Languages like VHDL are used in the design of FPGA and ASICs. Included is the history of VHDL, the benefits of utilizing the VHDL language, and a comparison of VHDL to Verilog, the other most common HDL.
- First VHDL design32:04
Once we understand why and how we use a hardware description language like VHDL, we must learn the structure, syntax, and rules for VHDL designs. In this lecture we learn the basics of a VHDL entity and architecture, as well as get a beginning look at the VHDL process. At the conclusion of this lecture we should be able to create a basic VHDL design.
- Acquiring a VHDL simulator3:21
We need a VHDL simulator for verifying our VHDL designs operate as we expect. In this discussion we look at the Intel Altera Quartus Lite Modelsim edition, as well as the Xilinx Vivado simulator. Either of these can be used for the lab work.
- Download and install Altera Modelsim1:39
A demonstration on downloading and installing the Altera Quartus Lite version of Modelsim
- Vivado Simulator Demonstration6:20
A demonstration for your first time with the Vivado Simulator from Xilinx
- Download and install Xilinx Vivado Simulator1:38
A demonstration on downloading and installing the Vivado Webpack with simulator included.
- Modelsim (Altera Quartus) Demonstration8:03
A demonstration on getting started with the Altera Quartus Lite version of Modelsim. Learn how to enter your design, compile, and then run the simulation.
- Acquire and Run GHDL Simulator8:35
Demonstration on how to acquire and run the GHDL Simulator
- Simulate with EDA Playground6:09
How to use the web based EDA playground
- Basic VHDL
- Lab 1 First VHDL Design
- Alternate Lab 1 Solution using Vivado6:10
Learn to implement a seven-bit temp mux in VHDL for the lab and verify it with the Vivado simulator, including creating an RTL architecture and testing with forced inputs.
- The VHDL Process19:39
Explore the VHDL process in detail, covering sensitivity lists, end-of-process signal assignments, and concurrent processes, then introduce integer and boolean types, and vector manipulation with aggregates and concatenation.
- Concurrent and Sequential Statements26:53
- VHDL Hierarchy21:53
Explore VHDL hierarchy by declaring components, instantiating them, and wiring with internal signals; build test benches to apply stimuli, simulate, and verify designs using explicit port maps.
- Testbench Demo with Vivado10:07
A demonstration of how to simulate a testbench and the design with the Vivado Simulator
- Testbench Demo with Modesim6:07
A demonstration of how to simulate a design with a TestBench in Modelsim
- Concurrent and Sequential VHDL Quiz
- Lab 2 - Add Logic to the thermostat design, create a testbench.
- Understanding the Flip-Flop25:32
Logic design is built from combinatorial logic and flip-flops. It is a combination of these structures that produce a complete design. We start by understanding the flip-flop. Its behavior and use, as well as how to define a flip-flop in VHDL.
- Synchronous Design Methodolgy21:06
The best FPGA and ASIC designs incorporate a synchronous design methodology. It is commonly referred to RTL design. In this lecture we discuss best practices for designing in a synchronous manner, and what asynchronous design pitfalls to avoid.
- RTL Styles22:33
We discuss the various RTL styles that are popular with FPGA and ASIC designers.
- RTL
- Lab 3 - Adding Flip Flops to the Thermostat design
- Multivalue logic (std_logic)18:26
A discussion of Multi-Value logic systems, with std_logic, std_ulogic, the most common signals types in RTL design
- Logic Arrays and Variables24:15
Explore composite types like standard logic vector, learn vector slicing and the differences between signals and variables in VHDL RTL design.
- State Machines33:50
Develop a practical understanding of VHDL state machines by creating enumerated types, modeling mealy and moore outputs, and exploring reset, transitions, and encoding options like binary and one-hot.
- VHDL Types
- Lab 4 - Creating a state machine
- VHDL logical and relational operators21:35
Explore VHDL logical and relational operators, emphasizing two-operand evaluation, bitwise vector operations, boolean versus standard logic, and shift, precedence, literals, and casting.
- Math Operators33:02
A discussion on how math is performed using VHDL, with multiple options and recommendations.
- Functions, Procedures, and Packages18:08
Explore how to use vhdl to design with overloaded functions, procedures, and packages, and organize libraries for test benches.
- VHDL Operators
- Lab 5 - Add counter to state machine
- Verification12:43
Verification is a significant portion of the design process. In VHDL we use sophisticated testbenches to verify the proper behavioral operation of our design. In this lecture we look at the various techniques used to sufficiently verify our design.s
- Self Checking Testbenches31:22
Self Checking Test Benches make regressive verification part of the design process. Self Checking Testbenches allow us to catch any latent faults as we add functionality to our designs.
- Verification
- Lab 6 - Self Checking Test Bench
Requirements
- Basic understanding of electronics and logic
Description
Twelve lectures, starting from the basics of VHDL, including the entity, architecture, and process. Explanations of the difference in sequential and concurrent VHDL. Discussions of good synchronous design methodology. Demonstrations on how to use the Altera Modelsim and Xilinx Vivado simulators. Six lab projects for hands-on experience, with the instructor showing how he would have done each lab.
Who this course is for:
- Beginner FPGA or ASIC designer